Heretofore, a stacked memory acquired by integrally molding a flash memory having 32-Mbit capacity and a static random access memory (SRAM) having 4-Mbit capacity in a fine pitch ball grid array (FBGA) type package in the form of a stacked chip has been provided. As for the flash memory and SRAM, the respective address input terminals and the respective data input/output terminals are connected to an input/output electrode of the FBGA type package in common. However, each control terminal is independent (for example, refer to “a stacked memory (stacked CSP) a flash memory+a RAM data sheet)”, type name LRS1380, [online], Dec. 10, 2001, Sharp Corporation, searched on Aug. 21, 2002, URL:http://www.sharp.co.jp/products/device/flash/cmlist.html).
There is also a stacked memory acquired by integrally molding a flash memory chip and a DRAM chip in a lead frame type package. In the stacked memory, respective address input terminals, respective data input/output terminals and respective control terminals of the flash memory and DRAM are connected to an input/output electrode of the package in common (for example, see FIGS. 1 and 17 in Japanese Patent Laid-Open No. H5 (1993)-299616 and refer to a specification of an European patent application No. 0566306).
There is also a system configured by a flash memory treated as a main memory device, a cache memory, a controller and CPU (for example, see FIG. 1 in Japanese Patent Laid-Open No. H7 (1995)-146820).
There is also a semiconductor memory configured by a flash memory, DRAM and a transfer control circuit (for example, see FIG. 2 in JP-A-2001-5723).